Marginal Change in Conduction Band Offset Due to Interface States in 4H-SiC MOS Devices Having Different Oxides

Authors

  • Ravi Kumar Chanana Retired Professor (Voluntarily)

DOI:

https://doi.org/10.63002/asrp.401.1294

Keywords:

Conduction Band Offset, Silicon Carbide, Silicon, Tunnelling, Interface states

Abstract

This short communication highlights the small variation in the conduction band offset (CBO) at the oxide/semiconductor interface of the metal-oxide-semiconductor (MOS) devices due to the variation in the interface state density at the interface known as Dit. In particular, a higher Dit gives a lower CBO and vice versa. In 4H-SiC MOS devices the CBO can change by up to 0.2 eV from 2.6 to 2.8 eV as observed experimentally.  Trap-assisted tunneling is attributed to the higher tunneling current in MOS devices having higher interface state density leading to lower CBO.

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Published

15-01-2026